Program
Session 1 (September 23, 16:30-18:05)
Invited 1
16:30-17:15
"A High-Level Approach for Parallelizing Legacy
Applications for Multiple Target Platforms"
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Ritu Arora (Texas Advanced Computing Center)
Abstract:
The tremendous growth and diversification in the area of computer architectures has resulted in novel HPC platforms with high theoretical peak performance. Adapting serial and parallel legacy applications to take advantage of the latest HPC platforms could be an effort-intensive activity that is proportional to the complexity of the applications, and the required parallel programming paradigm. Analyses of applications from diverse domains show that there are some standard operations that are required for adapting (or parallelizing) an application for latest computing platforms irrespective of the problem domain. Besides the standard operations, there are also some non-standard operations that are required (e.g., for-loop parallelization, data distribution, and orchestration of exchange of messages). These operations are referred to as non-standard because they are not a requirement for parallelizing all the applications according to a particular parallel programming paradigm but are specific to the problem domain or the type of data movement that is needed. Raising the level of abstraction of such standard and non-standard operations can result in a significant reduction in the time and effort required for adapting legacy applications for the various HPC platforms. In this talk, a high-level approach for semi-automatically parallelizing legacy applications for multiple target platforms will be presented. It will be shown that developing parallel applications at a high-level of abstraction does not necessarily lead to a significant loss in application performance.Bio:
Ritu Arora works as
an HPC researcher and consultant at the Texas Advanced Computing
Center (TACC). She is also a faculty member at the Department of
Statistics and Data Sciences at the University of Texas at Austin. She
has made contributions in the area of legacy HPC application migration
through her ongoing work on the framework for parallelizing legacy
applications in a user-guided manner. Her work on this framework is at
the crossroads of HPC and advanced software engineering techniques.
Ritu also provides HPC and Big Data consultancy to the users of the
national supercomputing resources through her role in XSEDE (Extreme
Science and Engineering Discovery Environment). The key areas of her
interest and expertise are HPC, fault-tolerance, domain-specific
languages, generative programming techniques, workflow automation, and
Big Data management. She received her Ph.D. in Computer and
Information Science from the University of Alabama at Birmingham.
17:15-17:40
"An Extension of OpenACC for Pipelined
Processing of Large Data on a GPU"
Fumihiko Ino, Akihito Nakano, and Kenichi Hagihara (Osaka University)
17:40-18:05
"OpenMP Parallelization Method using Compiler
Information of Automatic Optimization"
Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki
Kobayashi (Tohoku University)
Session 2 (September 24, 10:35-12:10)
Invited 2
10:35-11:20
"Dataflow based Task Execution through PaRSEC
for High Performance Computing Systems"
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Anthony Danalis (University of Tennessee, Knoxville)
Abstract:
Current system designs for High Performance Computing systems feature increasing processor and core counts, accelerators, and unpredictable memory access times. Utilizing such systems efficiently requires new programming paradigms. Solutions must react and adapt quickly to unexpected contentions and delays, and have the flexibility to rearrange the load balance to improve the resource utilization.
In this talk, I will present PaRSEC, a system centered on dataflow-based task execution. Task parallelism requires applications to be expressed as a task flow, i.e., a set of tasks that encompass the work that must be executed and the data dependencies between them. This strategy allows the algorithm to be decoupled from the data distribution and the underlying hardware, since the algorithm is entirely expressed as units of work and flows of data. This kind of layering provides a clear separation of concerns for architecture, algorithm, and data distribution. Developers benefit from this separation because they can focus solely on the algorithmic level without the constraints involved with programming for current and future hardware trends.
Bio:
Anthony
Danalis is currently a Research Scientist II with the Innovative
Computing Laboratory at the University of Tennessee, Knoxville. His
research interests come from the area of High Performance Computing.
Recently, his work has been focused on the subjects of Compiler
Analysis and Optimization, System Benchmarking, MPI, and Accelerators.
He received his Ph.D. in Computer Science from the University of
Delaware on Compiler Optimizations for HPC. Previously, he received an
M.Sc. from the University of Delaware and an M.Sc. from the University
of Crete, both on Computer Networks, and a B.Sc. in Physics from the
University of Crete.